1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a test circuit for a microcontroller unit (MCU).
2. Background of the Related Art
FIG. 1 is a schematic block diagram that illustrates a related art test mode setup circuit for a microcontroller unit (MCU). The related art test mode setup circuit is composed of a test pin 10.1 for receiving a test signal, a reset pin 10.2 for receiving a reset signal, a clock pin 10.3 for receiving a clock signal CLK and a test mode related circuit 10 for outputting a test mode related signal to an internal circuit when receiving the test signal over the test pin 10.1. The clock signal CLK is preferably generated using an oscillator (not shown).
In a normal mode, the test mode related circuit 10 is not connected with an internal circuit of the MCU. After a test mode is established, that is when a test signal inputted over the test pin 10.1 becomes active, the test mode related circuit 10 outputs the test mode related signal to the internal circuit to place the internal circuit in the test mode.
However, a MCU having a small number of pins has been produced in large numbers. Accordingly, as described above, the related art test mode setup circuit has various disadvantages. When the test pin is added to the MCU having the small number of pins in addition to essentially required pins such as the reset pin, a VDD pin, a VSS pin and a clock pin, a number of pins that are available for a user is decreased. Further, since the test pin is a pin that the user does not generally use (i.e., in normal operations), usability and applicability of the MCU is deteriorated.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide a test circuit for a MCU that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a test mode setup circuit for a MCU having a small number of pins.
Another object of the present invention is to provide a test circuit for a MCU that sets a test mode without adding a separate test pin.
Another object of the present invention is to provide a test mode setup circuit for a MCU that sets a test mode using only a reset pin and a clock pin.
To achieve at least the above-identified objects in a whole or in parts there is provided a test circuit for a microcontroller according to the present invention that includes a first pin receiving a first signal; a second pin receiving a second signal; and a test signal generating circuit that generates a test signal in response to a logical combination of the first signal and the second signal.
To further achieve at least the above-described objects in a whole or in parts there is provided a microcontroller unit according to the present invention that includes a clock pin that receives a clock signal; a reset pin that receives a reset signal; a test mode counter that is set and reset based on the clock signal and the reset signal to count the reset signal; and a decoder that activates a test mode flag when a count value of the test mode counter reaches a prescribed value.
To further achieve at least the above-described objects in a whole or in parts there is provided a test mode setup circuit for a microcontroller unit according to the present invention that includes a clock pin that receives a clock signal; a reset pin that receives a reset signal; a test signal generating circuit that counts the reset signal in accordance with a combination of the clock signal and the reset signal to generate a test signal, wherein the test signal generating circuit includes, a logic gate that logically processes the clock signal and the reset signal, a test mode counter that is set and reset in accordance with an output signal from the logic gate to count the reset signal, and a decoder that outputs the test signal when a count value from the test mode counter is a prescribed count value; and a test mode related circuit operated by the clock signal and the reset signal that enters an internal circuit into a test mode in accordance with the test signal from the test signal generating circuit.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.